This invention relates to static semiconductor memories for storing digital information; and more particularly it relates to such memories constructed out of Lambda diodes.
By definition, a static semiconductor memory is a memory in which stored information does not deteriorate as a function of time. When a digital "one" or a digital "zero" is stored in a static memory cell, that information remains unchanged until it is written differently or until power is removed from the memory cell. By comparison, information in a dynamic semiconductor memory must be periodically "refreshed;" otherwise, the information deteriorates and becomes lost.
Also by definition, a Lambda diode is a two-terminal device consisting of a pair of interconnected complementary depletion mode field effect transistors. One of those terminals is interconnected to the drain of the N-channel transistor and the gate of the P-channel transistor; and the other terminal is interconnected to the drain of the P-channel transistor and the gate of the N-channel transistor. Both the P-channel transistor and the N-channel transistor also have their sources interconnected together.
One prior art publication in which the Lambda diode is described is, "The Lambda Diode: A Versatile Negative Resistance Device," Kano et al., Electronics, June 26, 1975, pp. 105-109. There, the two transistors within the Lambda diode are described as being either junction field effect transistors (JFET) or insulated gate field effect transistors (IGFET). Also, the current-voltage (I-V) characteristic curve of the Lambda diode and several applications of the diode are described.
Those applications include a static memory cell. It is illustrated in FIG. 7 on page 109 of the publication and it is redrawn herein as FIG. 1. Note that the operation of that memory cell is not illustrated or described in the reference, but the operation is illustrated herein as FIG. 2 and is described below.
In FIG. 1, the Lambda diode is indicated by reference numeral 10; one of its terminals is indicated by reference numeral 11; and the other terminal is indicated by reference numeral 12. Symbol Q.sub.N indicates the N-channel transistor in the Lambda diode and symbol Q.sub.P indicates the P-channel transistor in the Lambda diode.
Current into terminal 11 is supplied through an enhancement mode P-channel transistor 13. That transistor has both its source and its gate connected to a conductor 14 to receive a bias voltage V.sub.dd. Thus, since transistor 13 is a P-channel device, that transistor is always turned off; and so only a leakage current passes through transistor 13 to terminal 11.
Terminal 11 is also where information is held in the memory cell. That information is in the form of either a "high" voltage or a "low" voltage. This voltage is stored during a write operation and read during a read operation by means of an access transistor 15, a bit line 16, and a word line 17.
Transistor 15 is an enhancement mode P-channel field effect transistor having its source connected to terminal 11, its drain connected to bit line 16, and its gate connected to word line 17. Bit line 16 is electrically connected to terminal 11 wherever the voltage on word line 17 is at least one threshold voltage below the voltage on bit line 16. Otherwise, terminal 11 is electrically isolated from bit line 16.
Consider now FIG. 2 wherein the detailed operation of the FIG. 1 memory cell is illustrated. There a curve 20 gives the I-V characteristics of the Lambda diode 10; and a curve 21 gives the I-V characteristics of transistor 13. Another curve 22 also exists, but it will be described subsequently in conjunction with a modification of the above memory cell.
Inspection of curve 20 shows that Lambda diode 10 exhibits a relatively low static resistance as the voltage on terminal 11 is increased from ground to a voltage V.sub.P. Thereafter, the Lambda diode exhibits a substantial increase in static resistance as the voltage on terminal 11 is further increased past voltage V.sub.P to a voltage V.sub.V. This increase is so large that the dynamic resistance of Lambda diode 10 is negative between voltages V.sub.P and V.sub.V. Then, as the voltage is increased still further to the bias voltage V.sub.dd, the Lambda diode exhibits a relatively high static resistance and passes only a leakage current.
This shape of curve 20 is explained as follows. When the voltage on terminal 11 is between zero volts and voltage V.sub.P, transistors Q.sub.N and Q.sub.P are both on. That is, the gate-to-source voltage of transistor Q.sub.N is negative but smaller in magnitude than that transistor's negative threshold V.sub.TN ; and the gate-to-source voltage of transistor Q.sub.P is positive but smaller in magnitude than that transistor's positive threshold V.sub.TP. Thus, as the voltage on terminal 11 increases from zero volts to voltage V.sub.P, the current through the Lambda diode N also increases.
By comparison, as the voltage on terminal 11 increases from voltage V.sub.P to voltage V.sub.V, transistors Q.sub.N and Q.sub.P both begin to turn off. And when the voltage on terminal 11 equals voltage V.sub.V, the gate-to-source voltage of transistor Q.sub.N and the gate-to-source voltage of transistor Q.sub.P respectively equal their threshold voltage. Voltage V.sub.V is thus defined as the magnitude of the threshold voltage for transistor Q.sub.N plus the magnitude of the threshold voltage for transistor Q.sub.P.
Finally, when the voltage on terminal 11 is between voltage V.sub.V and voltage V.sub.dd, transistors Q.sub.N and Q.sub.P are both turned off. Under this condition, only leakage current flows through Lambda diode 11.
Considering now curve 21, it can be seen that the current through transistor 13 is always very small, regardless of the voltage on terminal 11. This is because, as explained above, transistor 13 is always turned off. To repeat, transistor 13 is a P-channel device so it therefore needs a negative gate-to-source voltage to turn on. But since the gate of transistor 13 is connected to voltage V.sub.dd, the gate-to-source voltage of transistor 13 is always zero.
Inspection of FIG. 2 further shows that curves 20 and 21 intersect each other at three points labeled 23a, 23b, and 23c. Points 23a and 23c are stable operating states in the memory cell. In state 23a, a low voltage is stored in the cell; whereas in state 23c a high voltage is stored in the cell.
Point 23b, by comparison, is an unstable operating point; so it is not used to store information in the cell. Instead, point 23b is entered when information is read from the cell. In a read operation, bit line 16 is charged like a capacitor to the voltage at point 23b. Then transistor 15 is turned on so the charged bit line 16 is interconnected to node 11. Then, if a low voltage is stored on node 11, bit line 16 discharges slightly; whereas if a high voltage is stored on node 11, then bit line 16 charges slightly.
Suppose, for example, that a low voltage is stored at node 11. Then after bit line 16 is charged to the voltage at point 23b and transistor 15 is turned on, the voltage on bit line 16 will be reduced slightly to a voltage such as that indicated in FIG. 2 by reference numeral 23b'.
At that lower voltage, the current through Lambda diode 10 is greater than the current through transistor 13. This is evident from curves 20 and 21. And the extra current through Lambda diode 10 causes bit line 16 to discharge.
As a result, the voltage on bit line 16 drops even further. But at this new voltage, the current through Lambda diode 10 is even greater than the current through transistor 13. So bit line 16 discharges even faster. This process continues until after a relatively short time interval, point 23a is reached.
By comparison, suppose that a high voltage is stored in the memory cell. This voltage is also read by precharging bit line 16 to the voltage at point 23b and thereafter turning on transistor 15. When that occurs, the voltage on terminal 11 increases slightly to a voltage such as that indicated by reference numeral 23b" in FIG. 2.
Curves 20 and 21 show that at voltage 23b", transistor 13 supplies slightly more current than Lambda diode 10 can sink. Therefore, the extra current passing through transistor 13 operates to further charge bit line 16. Thus the voltage on bit line 16 rises slightly to another voltage. This process then continues until bit line 16 is charged to the voltage at point 23c.
But a problem with this charging operation is that the difference between the current supplied by transistor 13 and the current sunk by Lambda diode 10 is very small. This is evident by inspection of the righthand portion of curves 20 and 21 in FIG. 2. Therefore, only a small current is left over for charging bit line 16, and consequently it takes a long time to charge bit line 16 all the way up to the voltage at point 23c.
From the above, it is apparent that the "low" state of the FIG. 1 memory cell can be read relatively quickly; but the "high" state of the memory cell takes a long time to read. But since during a read operation it is not known whether a "high" state or a "low" state is stored, a long time interval must always be provided for the reading operation. Thus, the FIG. 1 memory is deficient in that the read takes too long.
This deficiency may be overcome by modifying the FIG. 1 memory such that the current through transistor 13 is greatly increased. That is, transistor 13 could intentionally be made to be very leaky. Or alternatively, transistor 13 could be replaced with a depletion mode transistor. In either case, the current through transistor 13 would be as indicated by curve 22 in FIG. 2 rather than curve 21.
Curve 22 intersects curve 20 at three points, 24a, 24b, and 24c. Points 24a and 24c are stable operating points and thus represent information stored in the memory cell; whereas point 24b is an unstable operating point. Information would be read from this modified memory cell by precharging the bit line to the voltage corresponding to point 24b, and thereafter turning on transistor 15.
Then the voltage on bit line 16 would move from point 24b to either the left or the right depending upon whether a "low" or a "high" voltage is stored in the memory cell. In either case, as the operating point is moved, a large difference would exist between the current supplied by transistor 13 and the current sunk by Lambda diode 10. Therefore, both a "low" state and a "high" state would be read relatively quickly.
But a problem with this modified memory cell is that at operating point 24a, a relatively high current passes through transistor 13 and Lambda diode 10. Therefore, the memory cell in that "low" state dissipates a relatively large amount of power. This, of course, is undesirable because memory cells typically are used in arrays comprising thousands of cells. Consequently, the maximum power dissipation of a memory chip can readily be exceeded if the power dissipation per cell is not made extremely small.
Accordingly, it is a primary object of the invention to provide an improved static semiconductor memory having both a relatively low power dissipation and relatively short read time in comparison to the prior art.